1. Field of the Invention
The invention relates generally to non-volatile semiconductor memory devices and more particularly to very high-density and high-speed split-gate non-volatile semiconductor memory devices.
2. Description of Related Art
Non-volatile semiconductor memory devices are known to store charges in an isolated gate (so called the floating gate) by means of either Fowler-Nordheim tunneling or hot-carrier injection through a thin insulator layer from the semiconductor substrate and to remove (so called erase) charges stored in an isolated gate by means of either Fowler-Nordheim tunneling or ultra-violet light through a thin insulator layer to the semiconductor substrate or another gate (so called the control gate or the erase gate) Aside from EPROMS using ultra-violet light for erase, almost all other non-volatile semiconductor memory devices are electrically erasable. The term xe2x80x9cflashxe2x80x9d in general refers to the ability to rapidly erase the stored charges with electrical pulses by means of Fowler-Nordheim tunneling. Basically, the cell size is a major concern for high-density mass storage applications and the device structure must be developed toward high program and erase efficiency with high reliability. The program,erase and read efficiency is mainly evaluated by voltage, current and time, and smaller in magnitude means better efficiency. Higher reliability implies higher endurance and higher retention; higher endurance means larger program and erase times (xe2x89xa7105) and higher retention means less stored-charges leakage due to any possible disturbs.
Based on the device structure, the prior arts can be basically divided into two catagories: stack-gate structure and split-gate structure. FIG. 1 shows a typical structure of the conventional stack-gate non-volatile memory devices and FIG. 2 shows a typical structure of the conventional split-gate non-volatile memory devices. The stack-gate non-volatile memory device shown in FIG. 1 includes a p-type substrate 100, and an n+-type source diffusion region 101 provided in the p-type substrate 100, and the double-diffused drain having a nxe2x88x92-type drain diffusion region 102 and a n+-type drain diffusion region 103 inserted in a nxe2x88x92-type drain diffusion region 102. A thin tunneling-oxide layer 104 is provided on the surface of the p-type substrate 100 having a thickness of approximately 100 Angstroms. A polycrystalline-silicon layer 105 acted as the floating gate is provided on the thin tunneling-oxide layer 104, and an inter-gate dielectric layer 106 using the ONO layer separates the floating gate 105 and the control gate 107 using the polycide layer.
The programming of this stack-gate non-volatile memory device shown in FIG. 1 is accomplished by applying a relatively high positive voltage of approximately 12 volts to the control gate and a moderately high voltage of approximately 9 volts to the source of the cell, and the drain is grounded. In general, the device is operated in saturation region and the channel-modulation region near the source is used to generate hot carriers in which hot-electrons with energy higher than the interface barrier between the conduction bands of the tunneling oxide and the semiconductor substrate are injected into the floating gate and stored there, and the hot holes generated produce the substrate current. Since most of channel carriers are collected by the positive source voltage, the injection efficiency is poor. Moreover, the optimization of source and channel profiles is needed to increase the programming efficiency without producing the reliability problems.
The erasing of the stack-gate non-volatile memory device shown in FIG. 1 is accomplished by applying a relatively high positive voltage of approximately 12 volts to the drain while the control gate is grounded and the source is usually floating. The stored electrons in the floating gate are tunneling from the floating gate to the drain by high electric field across thin tunneling gate oxide over the double-diffused drain. The above erasing can be slightly modified by reducing the applied voltage across the drain and substrate junction from 12 volts to 5 volts or below while the control gate is applied with a moderately high negative voltage of approximately-9 volts. The reduction of the drain voltage is mainly used to eliminate the band-to-band tunneling effects which may produce the undesirable hot-hole injection or holes trapped in the gate oxide. Apparently, the erase efficiency is dependent on the applied electric field across the thin tunneling oxide and the erase area. The higher electric field across the tunneling oxide needs higher applied voltage between the control gate and the drain or thinner tunneling-oxide layer; the larger erase area needs deeper double-diffused depth to produce larger overlapping area for thin gate oxide or to include the substrate and the overlapped source diffusion region for erase. However, the erase of stored electrons from the floating gate to the overlapped drain/source/the substrate is not self-limiting, the overerase problem is inevitable. Therefore, an adaptive erase technique using complicated circuitry and software to perform a series of erase and verify steps is used to prevent over-erasing cell shown in FIG. 1.
A typical split-gate non-volatile memory device shown in FIG. 2 includes a p-type substrate 110 and n+-type source and drain diffusion regions 118, 117 provided in the p-type substrate 110. A thin tunneling-oxide layer 111 of approximately 100 Angstroms in thickness is formed on the surface of a portion of the p-type substrate 110 and a portion of n+-type source diffusion region 118 under the polycrystalline-silicon floating gate 113. The floating gate 113 overlaps a portion of the source diffusion region 118 and a portion of the channel. A special shape of polycrystalline-silicon oxide 114 is formed on the polycrystalline-silicon floating gate 113 using the conventional LOCal-Oxidation of Silicon (LOCOS) technique. A dielectric layer 115 separates the sidewall of the polycrystalline-silicon floating gate 113 from the control gate 116, and a portion of the control gate 116 is formed on a thicker gate-oxide layer 112. The control-gate 116 overlaps a portion of the drain diffusion region 117 and a portion of the channel through a thicker gate-oxide layer 112. The conventional split-gate non-volatile memory device shown in FIG. 2 can be considered as two devices in series: one device is the floating-gate non-volatile memory transistor and the other device is a series enhancement-mode MOS transistor controlled by the control gate, and is recognized as 1.5 transistor device based on the lithographic point of view. Therefore, the prior art shown in FIG. 2 is not suitable for high-density mass-storage applications if the cost per bit is concerned. Moreover, the limitation of lithographic alignment tolerance of the control-gate results in another barrier for further device scaling.
The programming of the conventional split-gate non-volatile memory device shown in FIG. 2 is accomplished by applying a relatively low positive voltage of approximately 2 volts(threshold voltage of the control-gate MOS transistor)and a relatively high positive voltage of approximately 12 volts to the source of the cell, and the drain is grounded. The hot-carriers are generated by high lateral electric field under the gap between the floating gate and the control gate. The generated hot-electrons with energy higher than the interface barrier between the conduction bands of the silicon-oxide and the p-type substrate are injected into the floating gate and stored there, and the hot-holes generated produce the substrate current. Basically, the mechanism of the programming of the split-gate non-volatile memory device shown in FIG. 2 is similar to that of the stack-gate non-volatile memory device shown in FIG. 1. However, the channel current for programming which is controlled by the control gate is much smaller than that of the stack-gate non-volatile memory device shown in FIG. 1 and this is one of the advantages of the split-gate non-volatile memory device. The relatively high source voltage used is one of disadvantages as compared to that of the stack-gate non-volatile memory device, which is mainly due to 1.5 transistor used.
The erasing of the conventional split-gate non-volatile memory device shown in FIG. 2 is accomplished by applying a relatively high positive voltage of approximately 14 volts to the control gate while the source and the drain are grounded. The erasing is performed by using Fowler-Nordheim tunneling from the floating gate to the control gate through the side-wall injector along the edge of the floating gate and is self-limiting through the accumulation of positive charges on the injector of the floating gate. Therefore, the over-erasing doesn""t occur for the split-gate non-volatile memory device shown in FIG. 2, the erasing circuitry is then much simpler than that of the stack-gate non-volatile memory device shown in FIG. 1. The relatively high erasing voltage used is one of the disadvantages and the smiling effect due to the oxidation of the sidewall of the polycrystalline-silicon floating gate must be eliminated to prevent the reverse tunneling disturb.
From the above description, the stack-gate structure can be easily scaled by using the lithographic technique, but the programming efficiency is poor and most of source current is wasted, the over-erase problem needs complicated circuitry; the split-gate structure exhibits larger cell size and cannot be easily scaled by the prior art, and higher applied voltages are needed for program and erase, but the programming efficiency is high and the source current is smaller, the erasing is self-limiting and complicated circuitry is not required.
It is, therefore, an objective of this invention to provide a scalable split-gate non-volatile memory device for high-density and high-speed mass storage applications to overcome the disadvantages of the conventional split-gate non-volatile memory device.
The invention is divided into two parts. The first part of the invention discloses a method for simultaneously fabricating field-oxide isolation and floating gate of non-volatile semiconductor memory devices having high coupling ratio and embedded double-sides erase cathodes. The field isolation of the invention not only eliminates the field-implant encroachment and the bird""s beak extension into the active regions of minimum feature size designated for implementing non-volatile semiconductor memory device array but also reduces the isolation area, which accomplishes the first-step requirement for high-density non-volatile semiconductor memory implementation. Moreover, the lithographic masking step is reduced because the floating gate having the embedded double-sides erase cathodes and high coupling ratio is incorporated into the field isolation masking structure of the invention, resulting in the increasing throughput of manufacturing.
The second part of the invention discloses a method for fabricating scalable split-gate non-volatile semiconductor memory devices on the isolated structure disclosed in the first part of the invention. The scalable split-gate non-volatile semiconductor memory device is fabricated by the spacer formation technique without the conventional lithographic limitation, in which the floating-gate transistor and the control-gate transistor can be separately tailored to have a channel length much smaller than the minimum feature size of technology used. Therefore, the overall channel length of the fabricated split-gate non-volatile semiconductor memory device can be smaller than the minimum feature size of technology used and the major disadvantages of the conventional split-gate non-volatile semiconductor memory devices are removed. The self-aligned silicidation (SALICIDE) technique is applied to the control gate, the source/the common buried source, and the drain/the common buried drain of scalable split-gate non-volatile semiconductor memory devices; and to the gate, the source and the drain of peripheral MOS devices. Moreover, the self-aligned contacts are accomplished by forming the silicon-nitride spacers on the sidewalls of devices. As a result, the scalable split-gate non-volatile semiconductor memory device of the invention and the disclosed integration technology can be used to implement high-density and high-speed non-volatile memory system for mass storage applications.